module x74ls161_test(
Clk,
Reset_n,
A,
Q,
EP,
ET,
LD_n,
RCO,
clock
    );
input Clk;
input Reset_n;
input [3:0]A;
input LD_n;
input EP;
input ET;

output [3:0]Q;
output RCO;
output clock;

reg [24:0]cnt;
reg CP;

parameter MCNT=24_999_999;

assign clock=CP;

always@(posedge Clk or negedge Reset_n)
if(!Reset_n)
    cnt<=25'd0;
else if(cnt==MCNT)
        cnt<=25'd0;
     else
        cnt<=cnt+1'b1;

always@(posedge Clk or negedge Reset_n)
if(!Reset_n)
    CP<=0;    
else if(cnt==MCNT)
        CP=~CP;
     else
        CP<=CP;

x74ls161 x74ls161_inst0(
.CL_n(Reset_n),
.CP(CP),
.A(A),
.EP(EP),
.ET(ET),
.LD_n(LD_n),
.Q(Q),
.RCO(RCO)
);
    
endmodule